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01 / FPGA and Digital Architecture

CGRA on FPGA

A coarse-grained reconfigurable array that combines parallel FPGA execution with instruction-based reconfiguration.

Architecture

The system integrates an AXI4-Lite control path, arbiter, controller, 1024 × 64-bit instruction memory, and a 4 × 4 processing-element array.

Each processing element contains a 32-bit ALU, load-store unit, instruction register, dual data outputs, and 1024 × 32-bit local memory.

Data movement

A custom 64-bit instruction format and programmable row connections configure both PE operations and data routing without redesigning RTL for each kernel.