Concept overview
This is a sample/demo entry used to test the portfolio layout, not a completed professional project. It frames a CMOS LNA front end using a common-source or cascode topology, with input impedance matching and RF bias design.
The intended analysis covers S-parameters, noise, and stability, with parasitic-aware simulation considered before any layout work.
Scope boundaries
No fabricated chip or measured silicon performance is claimed. This entry exists to demonstrate layout and content structure only, and would be replaced with verified results if the design were carried through to silicon.