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01 / FPGA and Digital Architecture

LeNet-5 CNN Accelerator

An FPGA accelerator that maps the convolution, pooling, and classification stages of LeNet-5 into a hardware datapath.

Compute pipeline

The design turns repeated neural-network operations into dedicated hardware stages, reducing software instruction overhead and exposing fine-grained parallelism.

Implementation focus

The project explores data reuse, fixed hardware resources, and the throughput trade-offs involved in mapping a compact CNN onto an FPGA.