Concept overview
This is a sample/demo entry used to test the portfolio layout, not a completed professional project. It frames a transistor-level two-stage CMOS op-amp study: a differential input stage, a common-source gain stage, biasing, and Miller compensation for stability.
The intended analysis covers small-signal behaviour and AC and transient simulation across process, voltage, and temperature (PVT) corners.
Scope boundaries
No numerical gain, bandwidth, phase margin, power, or silicon results are included, since no verified data exists yet for this concept entry. Those figures would only be added once real simulation or measurement data is available.